Designing TSVs for 3D Integrated Circuits [electronic resource] / by Nauman Khan, Soha Hassoun.

Introduction -- Background -- Analysis and Mitigation of TSV-Induced Substrate Noise -- TSVs for Power Delivery -- Early Estimation of TSV Area for Power Delivery in 3-D ICs -- Carbon Nanotubes for Advancing TSV Technology -- Conclusions and Future Directions.

This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits. It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks. Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a oorplan are available. Finally, the authors explore the use of Carbon Nanotubes for power grid design as a futuristic alternative to Copper.

ZDB-2-ENG